The present invention relates to the field of serially programmable devices, and in particular to a method and apparatus for incorporating column redundancy into a serially programmable device.
To reduce pin count in an integrated circuit (IC), serial programming is often used. Because serial programming data is loaded into the IC in a continuous stream, only a single data input pin is required for programming. Typically, the programming data is loaded into a shift register within the IC. FIG. 1 shows a cascaded shift register 100 that has a typical register structure for a serially programmable IC. Shift register 100 includes flip flops 111, 112, 113, and 114, each of which includes an input terminal D, an output terminal Q, and a clock terminal CK. Output terminal Q of flip flop 111 is connected to input terminal D of flip flop 112, output terminal Q of flip flop 112 is connected to input terminal D of flip flop 113, and output terminal Q of flip flop 113 is connected to input terminal D of flip flop 114 to form the cascaded structure. Meanwhile, each clock terminal CK of flip-flops 111-114 is coupled to receive a clock signal CLOCK.
on each pulse of clock signal CLOCK, an input data value DIN is loaded into flip flop 111, the data previously stored in flip flop 111 is loaded into flip flop 112, the data previously stored in flip flop 112 is loaded into flip flop 113, and the data previously stored in flip flop 113 is loaded into flip flop 114. The data previously stored in flip-flop 114 is provided as an output data value DOUT. In this manner, serial data is shifted into (and out of) shift register 100. The data stored in shift register 100 can also be read out in parallel from the output terminal Qs of each of flip flops 111-114, as data values Q1-Q4, respectively.
Serially programmed memory ICs use this serial-in-parallel-out (SIPO) capability of a cascaded shift register to improve programming efficiency. In a typical non-volatile memory IC such as an electrically erasable programmable read only memory (EEPROM) or a FLASH memory, programming an individual memory cell in a memory array (typically using Fowler-Nordheim tunneling and/or channel hot electron injection) takes much longer than shifting data into a shift register. For example, 14 ms might be required to program a memory cell in an EEPROM or FLASH memory (using Fowler-Nordheim tunneling). In contrast, filling a shift register with new data only requires a number of clock cycles equal to the number of flip flops in the shift registerxe2x80x94e.g., if the system clock is running at 22 MHz and the shift register is a 4096-bit shift register, filling the shift register would only require 0.19 ms (=4096/22xc3x97106) Therefore, to minimize programming time, serial data is shifted into the shift register, and the contents of the shift register are then programmed into a particular address of the memory array as a single word. Since the memory cell programming for an entire row of the memory array can be performed in parallel, this xe2x80x9cpage modexe2x80x9d programming technique can significantly reduce overall programming time.
FIG. 2 shows a conventional serially programmable memory IC 200 that includes an input terminal 201, a register output terminal 202, a data register 210 connected between input terminal 201 and register output terminal 202, a bitline latch 211, a Mxc3x97N memory array 220, sense amplifiers 231, a data latch 232, a bit shifting multiplexer 233, and an output terminal 203. Mxc3x97N memory array 220 is made up of M rows (i.e., rows W0 through WM-1) and N columns (i.e., columns C0 through CN-1) of memory cells. To program a row of memory array 220, a programming bitstream DIN is shifted into data register 210 via input terminal 201. Data register 210 provides a serial programming path for IC 200xe2x80x94i.e., a data path into which a programming bitstream can be serially loaded, prior to a parallel programming operation. Once data register 210 is filled, the stored bitstream is loaded into bitline latch 211, after which the latched data is programmed into a selected row of memory array 220 in a page mode programming operation. To read out a word from memory array 220, the selected word data is latched into data latch 232 via sense amplifiers 231, and the latched data is then shifted out of output terminal 203 as a serial output data stream DOUT by bit shifting multiplexer 233. In this manner, the number of data input and output pins required by IC 200 can be minimized.
However, as memory arrays continue to increase in size, the denser memory structures become more susceptible to memory defects (such as a column short, bad trace, etc.). Therefore, to maintain a high production yield, it becomes increasingly desirable to provide redundancy in a memory arrayxe2x80x94i.e., include extra columns that can be used to replace defective columns. In the absence of such redundancy, a single bad memory cell can render an entire memory array unusable. Conventionally addressed memory arrays incorporate such redundant columns by simply addressing the appropriate redundant column instead of the defective column. However, in conventional serially programmable memory arrays, this type of random access is not available, making redundancy extremely difficult to incorporate.
For example, in FIG. 2, columns CN-1 and CN-2 could be redundant columns to be used if there are defects in any of columns C0 through CN-3 (which would then represent the xe2x80x9cprimary memory regionxe2x80x9d of memory array 220xe2x80x94i.e., the portion of memory array 220 in which data would be stored in the absence of array defects). In such an arrangement, replacing a defective column with column CN-1 would require that the flip flop in data register 210 associated with column CN-1 receive the data originally intended for the flip flop associated with the defective column. However, the flip-flops in a shift register (i.e., data register 210) are hardwired in a predetermined order, and so cannot be easily reordered to incorporate the redundant column in place of the defective column.
To overcome this limitation, conventional ICs sometimes include redundancy logic that counts clock cycles as data is shifted into the shift register. The redundancy logic uses the clock counts to determine whether a particular data bit is associated with a defective column, and if so, transfers that data bit to a redundant column. To function properly, this type of redundancy logic must know exactly when the program data begins shifting into the data register. However, in many cases, such program data timing knowledge is not available, so that conventional redundancy logic cannot be used.
For example, many modern ICs use the industry standard JTAG (Joint Test Action Group) interface for programming purposes. JTAG refers to IEEE standard 1149.1-1990 (includes IEEE Std 1149.1a-1993), published by the Institute of Electrical and Electronics Engineers, Inc. on Oct. 21, 1993 under ISBN 1-55937-350-4, herein incorporated by reference. IEEE standard 1149.1 defines a boundary scan test method for detecting bad connections (shorted pins, open pins, bad traces, etc.) in circuit boards. The JTAG interface includes a test data input (TDI) pin for loading serial test data into the data register of an IC, and this TDI pin is often used as a serial programming interface on many ICs. For example, input terminal 201 could represent a TDI pin in a JTAG-programmable IC (and register output pin could represent a TDO (test data output) pin to pass data out from data register 210).
Because conventional JTAG-based programming methods involve continuously shifting the programming data through multiple daisy-chained ICs (i.e., the TDO pin of an IC being connected to the TDI pin of a subsequent IC), none of the individual ICs has knowledge of when its own program data is being loaded into its shift register. Only when program data has filled the entire chain of ICs can an individual IC xe2x80x9cknowxe2x80x9d its specific program data. Therefore, conventional redundancy logic cannot be used in JTAG-compliant ICs.
Accordingly, it is desirable to provide a system and method for incorporating redundancy into a serially programmable IC without requiring specific knowledge about the address or timing of program data.
The invention provides a system and method for incorporating redundancy into a serially-programmable IC by dividing an input data register into discrete data register portions associated with column groupings (both primary and redundant) within a memory array. When a defective column(s) is detected among the primary columns of the memory array, bypass logic removes the data register portion associated with the defective column grouping (i.e., the primary column grouping including the defective column) from the serial programming path. To make up for this reduction in data register space, the bypass logic then incorporates a data register portion associated with a redundant column grouping into the serial programming path. In this manner, a defective column grouping is simply xe2x80x9cskippedxe2x80x9d during programming operations, with the programming bitstream being shifted into the redundant column groupings. This beneficially allows the programming bitstream to be shifted into the IC without any data reordering or address tracking.
According to an embodiment of the invention, a serially programmable IC can comprise a series of daisy-chained data register circuits, each data register circuit including a cascaded shift register and localized bypass logic for that shift register. The localized bypass logic can comprise a multiplexer that multiplexes the output of the data register circuit between the shift register output and the input of the data register circuit. Therefore, the multiplexer can either send the input of the data register circuit directly to the output (i.e., bypass the shift register) or connect the shift register between the input and output of the data register circuit. The control logic for the multiplexer can simply be a fuse that is programmed at the factory based on testing of the memory array.
If a defective column is detected, the data register circuit associated with the column grouping including the defective column is programmed to bypass its shift register, and one of the data register circuits associated with the redundant columns is enabled (i.e., the shift register in the redundant data register circuit is placed in the serial programming data path by its multiplexer).
Reading data from the memory array programmed in this manner simply involves reading out any data stored in redundant columns, and then reading out data stored in the primary columns, bypassing any columns bypassed during the programming operation. According to an embodiment of the invention, the IC can include an output control circuit performing the read operation. The output control circuit includes a defective address circuit for identifying the enabled redundant column groupings and bypassed primary column groupings. The defective address circuit can include programmable memories into which local addresses for the defective column groupings and redundancy enable indicators for the enabled redundant column groupings can be programmed (at the same time that the control circuits for the multiplexers in the data register circuits are programmed).
To perform a read operation, a redundant bit shifting multiplexer first shifts out the data stored in the redundant column groupings identified by the redundancy enable indicators as containing stored data. Then, a primary bit shifting multiplexer shifts out the remainder of the data word from the primary columns, skipping those primary column groupings identified by the local addresses in defective address circuit as including defective columns. In this manner, the stored data can be serially read out from the redundancy-enabled memory array.
The present invention will be more fully understood in view of the following description and drawings.